Data writing apparatus, data writing method, and program

ABSTRACT

Each of a plurality of storage devices (N- 1  to N-n) has a plurality of memory blocks for storing data. A data writing apparatus obtains error information which represents good blocks which can store data correctly, from the plurality of storage devices (N- 1  to N-n). The data writing apparatus determines a memory block in which data is to be written, in each of the plurality of storage devices (N- 1  to N-n), based on the obtained error information. The data writing apparatus controls the plurality of storage devices (N- 1  to N-n), and writes predetermined data in the determined memory blocks.

TECHNICAL FIELD

[0001] The present invention relates to an apparatus, a method, and aprogram for writing data in a storage device. Particularly, the presentinvention relates to an apparatus, a method and a program for writingsame data into a plurality of storage devices.

BACKGROUND ART

[0002] Flash memories known as small-sized storage devices are roughlyclassified into NOR type, NAND type, and AND type.

[0003] NOR type flash memories can be randomly accessed on a basis ofone byte unit. However, when compared to NAND type and AND type flashmemories, NOR type flash memories are expensive and have low integrateddensity.

[0004] On the other hand, since NAND type and AND type flash memoriesare low-cost and have high integrated density when compared to NOR typeflash memories, those flash memories are widely used. For example,TH58512FT (TOSHIBA) is known as one of AND type flash memories.

[0005] However, the ratios of defective memory blocks (memory blockswhich cannot store data correctly) included in all the memory blocksconstituting the memory areas of the NAND type and AND type flashmemories are intolerably large.

[0006] Accordingly, in many cases, when addressing a plurality of NANDtype (or AND type) flash memories in parallel to write same data,writing cannot be correctly performed.

[0007] Therefore, in order to write same data in a plurality of NANDtype (or AND type) flash memories, data is written in the plurality ofNAND type (or AND type) flash memories one by one in a sequential order,using a control signal such as a chip enable signal.

[0008] However, the above method is inefficient, and if NAND type (orAND type) flash memories in which data is to be written are existing ina large number, quite a long time is required to complete writing.

[0009] Therefore, it has been quite difficult to mass produce productsincluding NAND type (or AND type) flash memories in which predetermineddata is preinstalled.

DISCLOSURE OF INVENTION

[0010] Accordingly, an object of the present invention is to provide adata writing apparatus, a data writing method, and a program for writingsame data efficiently in a plurality of storage devices which might havedefective memory blocks.

[0011] To achieve the above object, a data writing apparatus accordingto a first aspect of the present invention is a data writing apparatusfor writing same data in a plurality of storage devices, wherein

[0012] each of the plurality of storage devices (N-1 to N-n) comprises:

[0013] a plurality of memory blocks which store data and errorinformation representing whether or not each of said plurality of memoryblocks is a good block which can store data correctly;

[0014] an error information supplier (22, 34, 35) which supplies thedata writing apparatus with the error information stored in theplurality of memory blocks; and

[0015] a data writer (22, 34, 35) which, in response to an instructionof the data writing apparatus, writes data in a memory block designatedby the data writing apparatus, and

[0016] the data writing apparatus comprises:

[0017] a block designator (12) which designates a memory block to whichdata is to be written for each of the plurality of storage devices (N-1to N-n), based on the error information supplied from the errorinformation supplier (22, 34, 35);

[0018] a data supplier (12) which supplies the plurality of storagedevices (N-1 to N-n) with data to be written; and

[0019] a writing instructor (12) which instructs the plurality ofstorage devices (N-1 to N-n) to write the data supplied by the datasupplier (12) in the memory blocks designated by the block designator(12).

[0020] According to this invention, since a memory block in which datais to be written is designated based on error information, it ispossible to write same data efficiently in a plurality of storagedevices which might have defective memory blocks.

[0021] Each of the plurality of storage devices (N-1 to N-n) may furthercomprise:

[0022] a first determiner (22, 34, 35) which determines whether or notthe data has been written correctly; and

[0023] a result supplier (22, 34, 35) which supplies the data writingapparatus with a determination result of the first determiner (22, 34,35).

[0024] The data writing apparatus may further comprise:

[0025] a second determiner (12) which determines whether or not there isany defective device among the plurality of storage devices (N-1 to N-n)to which the data has not been written correctly, based on thedetermination result supplied form the result supplier (22, 34, 35); and

[0026] a defective device identifier (12) which in a case where thesecond determiner (12) determines that there is any defective device,identifies the defective device.

[0027] The block designator (12) may designate another memory block towhich the data is to be written, in the defective device identified bythe defective device identifier (12) based on the error information.

[0028] The writing instructor (12) may instruct the defective device towrite the data supplied by the data supplier (12) in the another memoryblock designated by the block designator 12).

[0029] The block designator (12) may comprise:

[0030] a table generator (12) which generates a good block table listinggood blocks included in each of the plurality of storage devices (N-1 toN-n), based on the error information supplied from the error informationsupplier (22, 34, 35); and

[0031] a block determiner (12) which determines a memory block to whichthe data is to be written, based on the good block table.

[0032] The data writing apparatus may further comprise an informationupdating unit (12) which, in a case where the second determiner (12)determines that there is any defective device, updates the errorinformation stored in the plurality of memory blocks included in thedefective device.

[0033] The data writing apparatus may further comprise:

[0034] a third determiner (12) which determines whether or not there isany storage device which has no memory block left in which data can bewritten; and

[0035] a suspension unit (12) which suspends data writing, in a casewhere the third determiner (12) determines that there is any storagedevice which has no memory block left in which data can be written.

[0036] Each of the plurality of memory blocks may be allotted anaddress.

[0037] The block designator (12) may designate a memory block to whichdata is to be written, by outputting an address allotted to the memoryblock to which data is to be written.

[0038] The block designator (12) may divides the address into aplurality of parts, and outputs the plurality of parts one by one.

[0039] In a case where at least a part of the address to be output iscommon to at least two of the plurality of storage devices (N-1 to N-n),the block designator (12) may output the common part of the address tothe at least two storage devices simultaneously.

[0040] Each of the plurality of storage devices (N-1 to N-n) may beconstituted by a NAND type flash memory.

[0041] Each of the plurality of storage devices (N-1 to N-n) may beconstituted by an AND type flash memory.

[0042] A data writing method according to a second aspect of the presentinvention is a data writing method of writing same data in a pluralityof storage devices, wherein

[0043] each of the plurality of storage devices (N- 1 to N-n) comprises:

[0044] a plurality of memory blocks which store data and errorinformation representing whether or not each of the plurality of memoryblocks is a good block which can store data correctly; and

[0045] a data writer (22, 34, 35) which writes data in said plurality ofmemory blocks, and

[0046] the data writing method comprises:

[0047] a block designating step of designating a memory block in whichdata is to be written for each of the plurality of storage devices (N-1to N-n), based on the error information stored in said plurality ofmemory blocks;

[0048] a data supplying step of supplying the plurality of storagedevices (N-1 to N-n) with data to be written; and

[0049] a writing step of instructing the plurality of storage devices(N-1 to N-n) to write the data supplied in the data supplying step inthe memory block designated in the block designating step.

[0050] A program according to a third aspect of the present inventioncontrols a computer to function as a data writing apparatus which writessame data in a plurality of storage devices (N-1 to N-n) eachcomprising: a plurality of memory blocks which store data and errorinformation representing whether or not each of said plurality of memoryblocks is a good block which can store data correctly; an errorinformation supplier (22, 34, 35) which supplies the error informationstored in the plurality of memory blocks; and a data writer (22, 34, 35)which writes data in the plurality of memory blocks,

[0051] the data writing apparatus comprising:

[0052] a block determiner (12) which determines a memory block to whichdata is to be written for each of the plurality of storage devices (N-1to N-n), based on the error information supplied from the errorinformation supplier (22, 34, 35);

[0053] a data supplier (12) which supplies the plurality of storagedevices (N-1 to N-n) with data to be written; and

[0054] a writer (12) which, by controlling each of the plurality ofstorage devices (N-1 to N-n), writes the data supplied by the datasupplier (12) in the memory block determined by the block determiner(12).

BRIEF DESCRIPTION OF THE DRAWINGS

[0055] These objects and other objects and advantages of the presentinvention will become more apparent upon reading of the followingdetailed description and the accompanying drawings in which:

[0056]FIG. 1 is a diagram showing a structure of a flash memory writingapparatus according to a first embodiment;

[0057]FIG. 2 is a diagram showing a structure of a NAND flash memoryshown in FIG. 1;

[0058]FIG. 3 is a diagram showing a structure of a memory cell arrayconstituting the NAND flash memory shown in FIG. 2;

[0059]FIG. 4 is a flowchart showing a data reading process performed bya NAND flash memory controller which constitutes the flash memorywriting apparatus shown in FIG. 1;

[0060]FIG. 5 is a diagram showing signals to be output/received by theNAND flash memory controller in the data reading process shown in FIG.4;

[0061]FIG. 6 is a flowchart showing a data erasing process performed bythe NAND flash memory controller which constitutes the flash memorywriting apparatus shown in FIG. 1;

[0062]FIG. 7 is a diagram showing signals to be output/received by theNAND flash memory controller in the data erasing process shown in FIG.6;

[0063]FIG. 8 is a flowchart showing a data writing process performed bythe NAND flash memory controller which constitutes the flash memorywriting apparatus shown in FIG. 1;

[0064]FIG. 9 is a diagram showing signals to be output/received by theNAND flash memory controller in the data writing process shown in FIG.8;

[0065]FIGS. 10A and 10B are a flowchart showing a data writing processperformed by the AND flash memory controller when writing same data in aplurality of NAND flash memories;

[0066]FIG. 11 is a diagram showing signals to be output by the NANDflash memory controller in the data writing process shown in FIGS. 10Aand 10B;

[0067]FIG. 12 is a diagram showing a structure of a flash memory writingapparatus according to a second embodiment;

[0068]FIG. 13 is a diagram showing signals to be output by a NAND flashmemory controller which constitutes the flash memory writing apparatusshown in FIG. 12, when writing same data in a plurality of NAND flashmemories; and

[0069]FIGS. 14A and 14B respectively show examples of methods by which aNAND flash memory controller controls a same address to be acquired in aplurality of NAND flash memories.

BEST MODE FOR CARRYING OUT THE INVENTION

[0070] Next, a data writing apparatus and a data writing methodaccording to embodiments of the present invention will be explained, byemploying a flash memory writing apparatus as an example.

FIRST EMBODIMENT

[0071] A flash memory writing apparatus according to a fist embodimenthas a structure shown in FIG. 1, and writes same data in a n (n is aninteger equal to or greater than 2) number of NAND flash memories N-1 toN-n.

[0072] As shown in FIG. 1, the flash memory writing apparatus accordingthe first embodiment comprises a NAND flash memory controller (memorycontroller) CN, a bus B1, address latch enable (ALE) signal lines B2-1to B2-n, command latch enable (CLE) signal lines B3-1 to B3-n, readenable (RE) signal lines B4-1 to B4-n, and ready signal lines B5-1 toB5-n.

[0073] The memory controller CN is connected to the NAND flash memoriesN-1 to N-n equally through the bus B1. The bus B1 is constituted by adata/address bus having a bit width of plural bits, and a write enable(WE) signal line.

[0074] Further, the memory controller CN is connected to the NAND flashmemories N-1 to N-n separately through the ALE signal lines B2-1 toB2-n, the CLE signal lines B3-1 to B3-n, the RE signal lines B4-1 toB4-n, and the ready signal lines B5-1 to B5-n.

[0075] Specifically, the memory controller CN is connected to the NANDflash memory N-k (k is an arbitrary integer equal to or greater than 1and equal to or smaller than n) through the ALE signal line B2-k, theCLE signal line B3-k, the RE signal line B4-k, and the ready signal lineB5-k.

[0076] As shown in FIG. 1, the memory controller CN comprises a storage11, and a control unit 12, and performs writing, reading, and erasing ofdata on the NAND flash memories N-1 to N-n.

[0077] The storage 11 comprises a non-volatile storage 11A such as PROM(programmable Read Only Memory) or the like, and a volatile storage 11Bsuch as RAM (Random Access Memory) or the like.

[0078] The non-volatile storage 11A pre-stores a program for controllingthe operation of the control unit 12. The volatile storage 11B is usedas the work area of the control unit 12.

[0079] The control unit 12 is constituted by a CPU (Central ProcessingUnit) or the like, and operates in accordance with the program stored inthe storage 11.

[0080] The control unit 12 receives ready signals supplied from the NANDflash memories N-1 to N-n through the ready signal lines B5-1 to B5-n.The ready signals represent the states of operation of the NAND flashmemories N-1 to N-n.

[0081] The control unit 12 controls the operation of the respectiveflash memories N-1 to N-n based on the states of operation representedby the supplied ready signals.

[0082] Specifically, the control unit 12 outputs a command, data, and anaddress to the NAND flash memories N-1 to N-n equally through thedata/address bus of the bus B1. The command is for instructing the NANDflash memories N-1 to N-n to write, read, and erase data. The data isthe object to be written in the NAND flash memories N-1 to N-n. Theaddress represents a location to write in data, a storage location ofdata to be read, or a storage location of data to be erased, as will bedescribed later.

[0083] The control unit 12 outputs a WE signal to the NAND flashmemories N-1 to N-n equally through the WE signal line of the bus B1.The control unit 12 outputs an ALE signal through the ALE signal linesB2-1 to B2-n, a CLE signal through the CLE signal lines B3-1 to B3-n,and a RE signal through the RE signal lines B4-1 to B4-n to the NANDflash memories N-1 to N-n separately.

[0084] As will be described later, the WE signal, the ALE signal, the REsignal, and the CLE signal are combined together thereby to instructlatch timings (timings to obtain) of the above described command, data,and address to the NAND flash memories N-1 to N-n.

[0085] Next, the structure of the NAND flash memories N-1 to N-n will beexplained.

[0086] Each of the NAND flash memories N-1 to N-n is constituted by aNAND type EEPROM (Electrically Erasable/Programmable ROM).

[0087]FIG. 2 is a block diagram of a NAND flash memory N-k (k is anarbitrary integer equal to or greater than 1, and equal to or smallerthan n).

[0088] As shown in FIG. 2, the NAND flash memory N-k comprises adata/address bus 21, input/output control circuit 22, a command register23, a data register 24, an address register 25, a status register 26, amemory cell array 27, a row address buffer 28, a row address decoder 29,a column address buffer 30, a column address decoder 31, a sense amp 32,a high voltage generation circuit 33, a control circuit 34, and anoperation logic control circuit 35.

[0089] The data/address bus 21 is connected to the data/address bus ofthe bus B1.

[0090] The input/output control circuit 22 is connected to the memorycontroller CN through the data/address bus 21. The input/output controlcircuit 22 receives a command, data, and an address to be supplied fromthe memory controller CN. Also, the input/output control circuit 22outputs data read from the memory cell array 27, a later-describedoperation result to be stored in the status register 26, etc. to thememory controller CN.

[0091] The command register 23 stores a command received by theinput/output control circuit 22.

[0092] The data register 24 stores data received by the input/outputcontrol circuit 22, and data read from the memory cell array 27.

[0093] The address register 25 stores an address received by theinput/output control circuit 22.

[0094] The status register 26 stores results of operations executedunder the control of the memory controller CN.

[0095] The memory cell array 27 is formed of a plurality of memory cellsarranged in a matrix, and stores various data. The detailed structure ofthe memory cell array 27 will be described later.

[0096] The row address buffer 28, the row address decoder 29, the columnaddress buffer 30, and the column address decoder 31 convert an addressstored in the address register 25 into a row and column for specifyingthe location of a memory cell to or from which data is written, read, orerased. Then, the row address buffer 28, the row address decoder 29, thecolumn address buffer 30, and the column address decoder 31 select thememory cell located in the converted row and column. By this selection,data is written in, read from, or erased from the selected memory cell.

[0097] The sense amp 32 amplifies a signal representing data read fromthe memory cell array 27 by a predetermined amplification rate, andstores the data in the data register 24.

[0098] The high voltage generation circuit 33 supplies drive electricityto the memory cell array 27, the row address decoder 29, and the senseamp 32.

[0099] The control circuit 34 controls interior operation of the NANDflash memory N-k in accordance with a command stored in the commandregister 23. Due to this, the control circuit 34 writes data in, readsdata from, or erases data from the memory cell array 27.

[0100] Further, the control circuit 34 has a ready (R) terminal which isconnected to the ready signal line B5-k, and outputs a ready signalrepresenting an operational status (ready/busy) of the NAND flash memoryN-k to the memory controller CN.

[0101] Specifically, in a busy state (for example, during data writing,reading, or erasing), the control circuit 34 sets a level of the readysignal to an inactive level (for example, low level). In a ready state(for example, when data writing, reading, or erasing is finished), thecontrol circuit 34 sets the level of the ready signal to an active level(for example, high level).

[0102] The operation logic control circuit 35 has a WE terminal, a REterminal, an ALE terminal, and a CLE terminal. The WE terminal isconnected to the WE signal line of the bus B1. The RE terminal isconnected to the RE signal line B4-k. The ALE terminal is connected tothe ALE signal line B2-k. The CLE terminal is connected to the CLEsignal line B3-k.

[0103] The operation logic control circuit 35 controls the operations ofthe input/output control circuit 22 and the control circuit 34 inaccordance with a WE signal, a RE signal, an ALE signal, and a CLEsignal supplied from the memory controller CN.

[0104] Next, the structure of the memory cell array 27 described abovewill be explained.

[0105] Each memory cell constituting the memory cell array 27 hasstorage capacity of 1 byte.

[0106] The memory cells are logically arranged in a matrix of 131,072rows and 528 columns. In this case, the NAND flash memory N-k hasstorage capacity of about 69.2 megabytes.

[0107] 528 memory cells arranged in each row form a page having storagecapacity of 528 bytes, as shown in FIG. 3. That is, the storage area ofthe memory cell array 27 is formed of 131,072 pages. Memory cellsincluded in each page are given location numbers of 1 to 528sequentially.

[0108] The 131,072 pages are divided from the top by a unit of 32 pagesinto 4,096 blocks. In this case, each block has storage capacity of 16kilobytes. The 4,096 blocks are given block addresses of 1 to 4,096sequentially. Pages included in each block are given page addresses of 1to 32 sequentially.

[0109] As shown in FIG. 3, each page is formed of a data area accountingfor 512 bytes from the head, and a redundant area accounting for 16bytes at the tail.

[0110] An objective memory cell to and from which data is written orread is identified by an address (physical address) formed of a bitstream having 26 bits, for example.

[0111] The bottom 9 bits of the physical address represent a columnaddress for specifying a column in which the objective memory cell islocated, and the remaining top 17 bits represent a row address forspecifying a row in which the objective memory cell is located. Columnaddresses range from 1 to 512, and row addresses range from 1 to131,072.

[0112] Further, of the 17 bits representing the row address, the top 12bits represent a block address for specifying a block in which theobjective memory cell is included, and the remaining bottom 5 bitsrepresent a page address for specifying a page in which the objectivememory cell is included. Block addresses range from 1 to 4096, and pageaddresses range from 1 to 32.

[0113] In the data area of each page, various data such as user dataused by a user, a device driver executed by an external circuit, etc.are stored.

[0114] In the redundant area of each page, there is stored an errorcheck code for confirming that data (user data and device driver) storedin the data area of the corresponding page are not destroyed.

[0115] There is also stored an error flag described below in theredundant area of each page. However, an error flag does not have to bestored in all redundant areas. For example, an error flag may be storedin the redundant area of the top page (i.e., a page specified by a pageaddress “1”) of each block.

[0116] An error flag represents the quality of the block storing thiserror flag, namely a good block, a congenitally defective block, or apostnatally defective block.

[0117] A good block is a block which can store data correctly. Acongenitally defective block is a block which is determined by amanufacturer of the NAND flash memory N-k before shipping as incapableof storing data correctly. A postnatally defective block is a blockwhich is determined while the NAND flash memory N-k is used as incapableof storing data correctly.

[0118] There may further be stored in the redundant area of each page, aflag representing an attribute of data stored in the data area of thecorresponding page.

[0119] The value of an error flag indicative of a good block isdetermined such that it can be changed to another value representing apostnatally defective block by simply writing new data upon the existingdata in the redundant area. Therefore, the value of an error flag can beupdated without performing the process of erasing data in the redundantarea.

[0120] For example, an error flag may be formed of a bit stream of 1byte (8 bits). In this case, it may be set that a good block isrepresented by seven or more bits each indicative of a value “1”, apostnatally defective block is represented by two or more and six orless bits each indicative of a value “1”, and a congenitally defectiveblock is represented by seven or more bits each indicative of a value“0”.

[0121] By setting as described above, an error flag representing a goodblock can be changed to represent a postnatally defective block byrewriting a value “1” into a value “0”.

[0122] Next, an operation of the flash memory writing apparatusaccording to the first embodiment will be explained.

[0123] First, an explanation will be given of a case where the memorycontroller CN performs writing, reading, and erasing of data on the NANDflash memory N-k.

[0124] (1) Reading of Data

[0125]FIG. 4 is a flowchart showing a data reading process performed bythe memory controller CN (the control unit 12, to be more specific).

[0126] First, the memory controller CN outputs a read command forinstructing data reading to the NAND flash memory N-k through thedata/address bus of the bus B1 (step S101).

[0127] At this time, the memory controller CN outputs a WE signal havingan active level through the WE signal line of the bus B1, and a CLEsignal having an active level through the CLE signal line B3-k to theNAND flash memory N-k. Specifically, as shown in FIG. 5, the memorycontroller CN sets the levels of both of the WE signal and the CLEsignal to active levels in synchronization with the timing of outputtingthe read command (Com-R).

[0128] Due to this, the memory controller CN controls the output readcommand to be acquired in the NAND flash memory N-k.

[0129] The NAND flash memory N-k acquires the supplied read command atthe timing the levels of the WE signal and CLE signal being suppliedfrom the memory controller CN change to active levels, and stores theread command in the command register 23.

[0130] Then, the memory controller CN outputs a physical addressrepresenting the location of the head memory cell of a page in which thedata to be read is stored to the NAND flash memory N-k (step S102).Specifically, the memory controller CN outputs a bit stream made up of ablock address, a page address and a column address as a physicaladdress.

[0131] Note that the head memory cell is a memory cell having an addressof the smallest value among the values representing addresses of thememory cells storing the data to be read.

[0132] At this time, the memory controller CN outputs a WE signal havingan active level through the WE signal line of the bus B1, and an ALEsignal having an active level through the ALE signal line B2-k to theNAND flash memory N-k. Specifically, as shown in FIG. 5, the memorycontroller CN sets the levels of the WE signal and the ALE signal toactive levels in synchronization with the timing of outputting thephysical address (ADD).

[0133] Due to this, the memory controller CN controls the outputphysical address to be acquired in the NAND flash memory N-k.

[0134] The NAND flash memory N-k acquires the supplied physical addressat the timing the levels of the WE signal and ALE signal being suppliedfrom the memory controller CN become active levels, and stores theacquired physical address in the address register 25.

[0135] The NAND flash memory N-k reads data from the head memory cellspecified by the physical address stored in the address register 25 andsequentially from the following memory cells in accordance with the readcommand stored in the command register 23. Specifically, the NAND flashmemory N-k reads data in the page where the specified head memory cellis included one memory cell by one (i.e., one byte by one) in the orderof the head memory cell to the next.

[0136] For example, in a case where data of one page is to be read, theNAND flash memory N-k reads data from the head of the page one byte byone over 528 times.

[0137] Then, the NAND flash memory N-k sequentially stores the read datain the data register 24.

[0138] In the meantime, the NAND flash memory N-k outputs a ready signalhaving an inactive level to the memory controller CN through the readysignal line B5-k, as shown in FIG. 5. When reading of data is completed,the NAND flash memory N-k outputs a ready signal having an active levelto the memory controller CN through the ready signal line B5-k.

[0139] The memory controller CN determines whether or not the level ofthe ready signal supplied through the ready signal line B5-k has changedfrom the inactive level to the active level (step S103). Based on this,the memory controller CN determines whether reading of data is completedor not.

[0140] In a case where it is determined that the level has not changedto the active level (step S103; NO), the memory controller CN determinesthat the data is now being read, and performs the process of step S103.

[0141] On the contrary, in a case where it is determined that the levelhas changed to the active level (step S103; YES), the memory controllerCN determines that reading of data is completed. Then, as shown in FIG.5, the memory controller CN outputs a RE signal having an active levelto the NAND flash memory N-k through the RE signal line B4-k (stepS104). The memory controller CN instructs the NAND flash memory N-k tooutput the data by setting the level of the RE signal to the activelevel.

[0142] In response to the RE signal having the active level and suppliedfrom the memory controller CN, the NAND flash memory N-k outputs thedata stored in the data register 24 to the memory controller CN throughthe data/address bus 21.

[0143] The memory controller CN reads data stored in the memory cellarray 27 of the NAND flash memory N-k in the way described above.

[0144] (2) Erasing of Data

[0145]FIG. 6 is a flowchart showing a data erasing process performed bythe memory controller CN (specifically, the control unit 12).

[0146] First, the memory controller CN outputs an erase command forinstructing erasing of data to the NAND flash memory N-k through thedata/address bus of the bus B1 (step S201).

[0147] At this time, the memory controller CN outputs a WE signal and aCLE signal both having an active level to the NAND flash memory N-k insynchronization with the timing of outputting the erase command (Com-E),as shown in FIG. 7. By doing so, the memory controller CN controls theoutput erase command to be acquired in the NAND flash memory N-k.

[0148] The NAND flash memory N-k acquires the supplied erase commandsynchronously with the timing at which the levels of the WE signal andCLE signal change to the active level, and stores the erase command inthe command register 23.

[0149] Then, the memory controller CN outputs a block address forspecifying the block storing the data to be erased to the NAND flashmemory N-k through the data/address bus of the bus B1 (step S202).

[0150] At this time, as shown in FIG. 7, the memory controller CNoutputs a WE signal and an ALE signal both having an active level to theNAND flash memory N-k in synchronization with the timing of outputtingthe block address (ADD). Thus, the memory controller CN controls theoutput block address to be acquired in the NAND flash memory N-k.

[0151] The NAND flash memory N-k acquires the supplied block address atthe timing the levels of the WE signal and ALE signal change to theactive level, and stores the block address in the address register 25.

[0152] Afterwards, the memory controller CN outputs an erase executingcommand for instructing start of data erasing to the NAND flash memoryN-k through the data/address bus of the bus B1 (step S203).

[0153] At this time, the memory controller CN outputs a WE signal and aCLE signal both having an active level to the NAND flash memory N-k insynchronization with the timing of outputting the erase executingcommand (Com-ES), likewise the above case.

[0154] In response to the supplied erase executing command at the timingthe levels of the WE signal and CLE signal change to the active level,the NAND flash memory N-k erases the data stored in the block specifiedby the block address stored in the address register 25.

[0155] Specifically, the NAND flash memory resets all the memory cellsincluded in the specified block address, i.e., sets the stored values ofall the memory cells to “1”.

[0156] As shown in FIG. 7, while data is being erased, the NAND flashmemory N-k sets the level of the ready signal to an inactive level.

[0157] In the way described above, the data stored in the NAND flashmemory N-k is erased by one block unit.

[0158] (3) Writing of Data

[0159]FIG. 8 is a flowchart showing a data writing process performed bythe memory controller CN (specifically, the control unit 12).

[0160] First, the memory controller CN outputs a store command forinstructing storing of data to the NAND flash memory N-k through thedata/address bus of the bus B1 (step S301).

[0161] At this time, the memory controller CN sets the levels of a WEsignal and a CLE signal to be output to the NAND flash memory N-k to anactive level in synchronization with the timing of outputting the storecommand (Com-S), as shown in FIG. 9. Thus, the memory controller CNcontrols the output store command to be acquired in the NAND flashmemory N-k.

[0162] The NAND flash memory N-k acquires the supplied store command atthe timing the levels of the WE signal and CLE signal change to theactive level, and stores the store command in the command register 23.

[0163] Then, the memory controller CN outputs a physical addressindicating the location of the head memory cell in a page in which datais to be written to the NAND flash memory N-k through the data/addressbus of the bus B1 (step S302).

[0164] Note that a head memory cell is a memory cell having the smallestvalue of the address among values of addresses of all the memory cellsinto which data is to be written.

[0165] At this time, the memory controller CN divides the physicaladdress into four parts (ADD-1, ADD-2, ADD-3, ADD4) and separatelyoutputs those parts, as shown in FIG. 9. Specifically, the memorycontroller CN divides the bit stream made up of a block address, a pageaddress, and a column address into four, and then outputs those fourparts.

[0166] Further, each time a physical address part is output, the memorycontroller CN a WE signal and an ALE signal both having an active levelto the NAND flash memory N-k, likewise the above case.

[0167] The NAND flash memory N-k sequentially acquires the addresses(ADD-1 to ADD-4) supplied at the timings the levels of the WE signal andALE signal change to the active level, and stores the addresses in theaddress register 25.

[0168] Then, the memory controller CN outputs data to be written onebyte by one to the NAND flash memory N-k through the data/address bus ofthe bus B1 (step S303).

[0169] At this time, the memory controller CN outputs a WE signal havingan active level to the NAND flash memory N-k through the WE signal lineof the bus B1, each time data is output, as shown in FIG. 9. Due tothis, the memory controller CN controls the output data to be acquiredin the NAND flash memory N-k.

[0170] The NAND flash memory N-k acquires data supplied through thedata/address bus 21 each time the level of the WE signal changes to theactive level, and stores the data in the data register 24.

[0171] Afterwards, the memory controller CN outputs a write command forinstructing start of data writing to the NAND flash memory N-k throughthe data/address bus of the bus B1 (step S304).

[0172] At this time, the memory controller sets the levels of a WEsignal and a CLE signal to be output to the NAND flash memory N-k to anactive level in synchronization with the timing of outputting the writecommand (Com-W), likewise the above case.

[0173] In response to the supplied write command at the timing thelevels of the WE signal and CLE signal change to the active level, theNAND flash memory N-k stores the data to be written now stored in dataregister 24 in the memory cell array 27.

[0174] Specifically, the NAND flash memory N-k stores data in the headmemory cell specified by the address stored in the address register 25and in the following memory cells sequentially.

[0175] Meanwhile, the NAND flash memory N-k sets the level of a readysignal to an inactive level, and after writing of data is completed,sets back the level of the ready signal to the active level, as shown inFIG. 9.

[0176] In the way described above, data to be written is written in theNAND flash memory N-k.

[0177] (4) Writing of Data to NAND Flash Memories N-1 to N-n

[0178] Next, explanation will be given of a case where the memorycontroller CN writes same data in the NAND flash memories N-1 to N-n.

[0179]FIGS. 10A and 10B are a flowchart showing a data writing processperformed by the memory controller CN (specifically, the control unit12) when writing same data in the NAND flash memories N-1 to N-n.

[0180] First, the memory controller CN generates data (a good blocktable) representing all good blocks included in the NAND flash memoriesN-1 to N-n. For example, the good block table represents block addressesof good blocks the NAND flash memories N-1 to N-n respectively include.Then, the memory controller CN stores the generated good block table inthe volatile storage 11B (step S401).

[0181] Specifically, the memory controller CN reads an error flag storedin each block of the NAND flash memories N-1 to N-n, by following thesame way as “(1) Reading of Data” described above. Then, the memorycontroller CN generates the good block table based on the valuesrepresented by the read error flags.

[0182] Then, the memory controller CN declares usage of a variable DATA#for determining a block in which data is to be written. Specifically,the memory controller CN secures a storage area for storing the value ofthe variable DATA# in the volatile storage 11B. Then, the memorycontroller CN sets the value of the variable DATA# to “0” (step S402).

[0183] Next, the memory controller CN secures a storage area for storingdata which amounts to one block and which is to be stored in the NANDflash memories N-1 to N-n in the volatile storage 11B. Then, the memorycontroller CN stores data of one block which is to be written, in thesecured storage area (data depositing area) by controlling anon-illustrated circuit for storage controlling (step S403).

[0184] Then, the memory controller CN increments the value of thevariable DATA# by 1 (step S404).

[0185] Then, the memory controller CN refers to the good block tablegenerated in step S401, and determines the objective block in which thedata of one block is to be written, for each of the NAND flash memoriesN-1 to N-n (step S405).

[0186] Specifically, in a case where the present value of the variableDATA# is “d”, the memory controller CN determines a good block whoseblock address is the “d-th” smallest of all the good blocks included ineach of the NAND flash memories N-1 to N-n, as the objective block.

[0187] Then, the memory controller CN declares usage of a variable PAGE#for determining the objective page in which the data is to be written.Specifically, the memory controller CN secures a storage area forstoring the value of the variable PAGE# in the volatile storage 11B.Then, the memory controller CN sets the value of the variable PAGE# to“0” (step S406).

[0188] Then, the memory controller CN determines data which amounts toone page and is to be written in the objective page from the data storedin the data depositing area (step S407).

[0189] Then, the memory controller CN increments the variable PAGE# by 1(step S408). The objective page in which data is to be written isdetermined by the variable PAGE#. That is, in a case where the variablePAGE# represents “2”, a page having a page address of “2” is determinedas the objective page.

[0190] Afterwards, the memory controller CN writes the data of one pagedetermined in step S407 in the objective page included in the objectiveblock of each of the NAND flash memories N-1 to N-n (step S409).

[0191] Specifically, the memory controller CN writes the data of onepage in the NAND flash memories N-1 to N-n likewise “(3) Writing ofData” described above.

[0192] First, as shown in FIG. 11, the memory controller CN outputs astore command (Com-S) to the NAND flash memories N-1 to N-n through thedata/address bus of the bus B1.

[0193] At this time, the memory controller CN outputs a WE signal havingan active level through the data/address bus of the bus B1, and a CLEsignal having an active level through the CLE signal lines B3-1 to B1-nto the NAND flash memories N-1 to N-n. Thus, the memory controller CNcontrols the output store command to be acquired in all of the NANDflash memories N-1 to N-n.

[0194] Then, the memory controller CN outputs a physical addressindicating the location of the head memory cell included in each of theobjective pages through the data/address bus of the bus B1.

[0195] However, the physical addresses of the head memory cells are notalways the same among the NAND flash memories N-1 to N-n. Therefore, asshown in FIG. 11, the memory controller CN outputs the physicaladdresses (ADD(1) to ADD(n)) of the head memory cells respectivelyincluded in the NAND flash memories N-1 to N-n one by one atpredetermined intervals.

[0196] Further, the memory controller CN outputs a WE signal and an ALEsignal both having an active level, each time it outputs a physicaladdress. At this time, as shown in FIG. 11, the memory controller CNswitches the outputting routes of the ALE signal having the active levelin accordance with the NAND flash memories to receive the physicaladdresses.

[0197] For example, in a case where the physical address ADD(1) of thehead memory cell included in the NAND flash memory N-1 is to be output,the memory controller CN outputs the ALE signal having the active levelto the NAND flash memory N-1 through the ALE signal line B2-1. In a casewhere the physical address ADD(k) of the head memory cell included inthe NAND flash memory N-k is to be output, the memory controller CNoutputs the ALE signal having the active level to the NAND flash memoryN-k through the ALE signal line B2-k.

[0198] Each of the NAND flash memories N-1 to N-n acquires the suppliedphysical address at the timing the ALE signal supplied to itself changesto the active level, and stores the physical address in the addressregister 25.

[0199] Although omitted in FIG. 11, the memory controller CN divides onephysical address into four, and then outputs them, as described in “(3)Writing of Data” described above.

[0200] Afterwards, the memory controller CN outputs the data of one pagedetermined in step S407 one byte by one to the NAND flash memories N-1to N-n through the data/address bus of the bus B1.

[0201] At this time, as shown in FIG. 11, the memory controller CNoutputs a WE signal having an active level to the NAND flash memoriesN-1 to N-n through the data/address bus of the bus B1, each time itoutputs data.

[0202] Due to this, the NAND flash memories N-1 to N-n acquire thesupplied data each time the level of the WE signal changes to the activelevel, and sequentially store the data in the data register 24.

[0203] After outputting the data of one page, the memory controller CNoutputs a write command (Com-W) to the NAND flash memories N-1 to N-nthrough the data/address bus of the bus B1, as shown in FIG. 11.

[0204] Also in this case, the memory controller CN outputs a WE signalhaving an active level through the data/address bus of the bus B1, and aCLE signal having an active level through the CLE signal lines B3-1 toB3-n to the NAND flash memories N-1 to N-n, likewise the above case.

[0205] In response to the supplied write command at the timing thelevels of the WE signal and CLE signal change to the active level, eachof the NAND flash memories N-1 to N-n writes the data of one page storedin the data register 24 in the memory cell array 27.

[0206] At this time, each of the NAND flash memories N-1 to N-n writesthe data stored in the data register 24 in the head memory cellspecified by the physical address stored in the address register 25 andin the following memory cells in this order one byte by one, likewisethe above case.

[0207] In the meantime, each of the NAND flash memories N-1 to N-noutputs a ready signal having an inactive level to the memory controllerCN, likewise the above case.

[0208] Further, each of the NAND flash memories N-1 to N-n determineswhether or not the data stored in the data register 24 is equal to thedata written in the memory cells, while writing the data. Based on this,each of the NAND flash memories N-1 to N-n determines whether or not thedata has been written correctly in a predetermined period of time, or ina predetermined number of times.

[0209] Then, each of the NAND flash memories N-1 to N-n stores thedetermination result in the status register 26. Specifically, each ofthe NAND flash memories N-1 to N-n stores a status bit representing thatwriting is successful (Pass) in the status register 26 in a case whereit is determined that the data has been written correctly. Each of theNAND flash memories N-1 to N-n stores a status bit representing thatwriting is unsuccessful (Fail) in the status register 26 in a case whereit is determined that the data has not been written correctly.

[0210] On the other hand, the memory controller CN determines whether ornot writing of data has been completed, based on the level of the readysignal supplied from each of the NAND flash memories N-1 to N-n,likewise the above case.

[0211] Then, when it is determined that writing of data has beencompleted, the memory controller CN determines whether or not writing ofdata is successful in all of the NAND flash memories N-1 to N-n (stepS410).

[0212] Specifically, the memory controller CN outputs a status readcommand for instructing output of the determination result stored in thestatus register 26 to the NAND flash memories N-1 to N-n through thedata/address bus of the bus B1. Then, the memory controller CN outputs aRE signal having an active level to the NAND flash memories N-1 to N-nthrough the RE signal lines B4-1 to B4-n.

[0213] When supplied with the status read command and the RE signalhaving the active level, each of the NAND flash memories N-1 to N-noutputs the value of the status bit stored in the status register 26, tothe memory controller CN.

[0214] The memory controller CN determines whether or not there is anyNAND flash memory that has failed in writing the data, based on thesupplied values of the status bits. Due to this, the memory controllerCN determines whether or not writing of data is successful in all of theNAND flash memories N-1 to N-n.

[0215] When it is determined that writing of data is not successful(step S410; NO), the memory controller CN specifies the NAND flashmemory that has failed in writing the data based on the supplied valuesof the status bits. Then, the memory controller CN specifies theobjective block included in the NAND flash memory that has failed inwriting of the data, as a postnatally defective block (step S411).

[0216] Then, the memory controller CN writes an error flag indicating apostnatally defective block, in the redundant area of each page or thetop page included in the specified postnatally defective block (stepS412).

[0217] Then, the memory controller CN updates (or regenerates) the abovedescribed good block table (step S413). Therefore, information regardingthe specified postnatally defective block is deleted from the good blocktable.

[0218] Afterwards, the memory controller CN refers to the updated goodblock table, and sets a block whose block address is the smallest secondto that of the postnatally defective block as an objective block. Then,the memory controller CN writes the data which should have already beenwritten in the newly set objective block (step S414), and performs alater-described process of step S415.

[0219] On the contrary, in a case where it is determined in step S410that writing of data is successful in all of the NAND flash memories N-1to N-n (step S410; YES), the memory controller CN determines whether ornot the objective page is the last page of the objective block (stepS415). Specifically, the memory controller CN determines whether or notthe value of the variable PAGE# is equal to the number of pages includedin one block.

[0220] In a case where it is determined that the objective page is notthe last page (step S415; NO), the memory controller CN moves to theprocess of step S407.

[0221] On the contrary, when it is determined that the objective page isthe last page (step S415; YES), the memory controller CN determineswhether or not all the data to be written has been written (step S416).

[0222] When it is determined that not all the data has been written(step S416; NO), the memory controller CN moves to the process of stepS403. Then, the memory controller CN writes the data yet unwritten inthe NAND flash memories N-1 to N-n.

[0223] On the contrary, when it is determined that all the data has beenwritten (step S416; YES), the memory controller CN ends the data writingprocess.

[0224] As described above, since writing of data is performed whilewhether such data is written successfully is determined, the same datacan be efficiently written in the NAND flash memories N-1 to N-n.

SECOND EMBODIMENT

[0225] Next, a flash memory writing apparatus according to a secondembodiment of the present invention will now be explained with referenceto the drawings.

[0226] As shown in FIG. 12, the flash memory writing apparatus accordingto the second embodiment comprises a NAND flash memory controller(memory controller) CN, read enable (RE) signal lines B4-1 to B4-n,ready (R) signal lines B5-1 to B5-n, write enable (WE) signal lines B6-1to B6-n, and a bus B7.

[0227] The RE signal line B4-k (k is an integer equal to or greater than1 and equal to or smaller than n) is connected to a RE terminal of aNAND flash memory N-k.

[0228] The ready signal line B5-k is connected to a ready terminal ofthe NAND flash memory N-k.

[0229] The WE signal line B6-k is connected to a WE terminal of the NANDflash memory N-k.

[0230] The bus B7 comprises a data/address bus, an address latch enable(ALE) signal line, and a command latch enable (CLE) signal line.

[0231] The data/address bus is connected to data/address buses 21 ofNAND flash memories N-1 to N-n.

[0232] The ALE signal line is connected to ALE terminals of the NANDflash memories N-1 to N-n.

[0233] The CLE signal line is connected to CLE terminals of the NANDflash memories N-1 to N-n.

[0234] The memory controller CN is connected equally to the NAND flashmemories N-1 to N-n through the bus B7.

[0235] Further, the memory controller CN is connected separately to theNAND flash memories N-1 to N-n through the RE signal lines B4-1 to B4-n,the ready signal lines B5-1 to B5-n, and the WE signal lines B6-1 toB6-n.

[0236] The structure of the flash memory writing apparatus issubstantially the same as that of the first embodiment, except the abovedescribed points.

[0237] Next, operations of the memory controller CN when writing samedata in the NAND flash memories N-1 to N-n will be explained.

[0238] As shown in FIG. 13, the memory controller CN outputs a storecommand (Com-S) first.

[0239] At this time, the memory controller CN outputs a CLE signalhaving an active level through the CLE signal line of the bus B7, and aWE signal having an active level through the WE signal lines B6-1 toB6-n to the NAND flash memories N-1 to N-n. Thus, the memory controllerCN controls the output store command to be acquired in all of the NANDflash memories N-1 to N-n.

[0240] Then, the memory controller CN outputs physical addressesindicating the locations of the head memory cells included in theobjective pages in which data is to be written, through the data/addressbus of the bus B7.

[0241] At this time, the memory controller CN outputs the physicaladdresses (ADD(1) to ADD(n)) of the head memory cells included in theNAND flash memories N-1 to N-n one by one at predetermined intervals,likewise the first embodiment.

[0242] Further, the memory controller CN outputs a WE signal and an ALEsignal both having an active level to the NAND flash memories N-1 toN-n, each time it outputs a physical address. At this time, as shown inFIG. 13, the memory controller CN switches the outputting routes of theWE signal having the active level in accordance with the NANd flashmemories N-1 to N-n to receive the physical address.

[0243] For example, in a case where the physical address ADD(1) of thehead memory cell included in the NAND flash memory N-1 is to be output,the memory controller CN outputs the WE signal having the active levelto the NAND flash memory N-1 through the WE signal line B6-1. In a casewhere the physical address ADD(k) of the head memory cell included inthe NAND flash memory N-k is to be output, the memory controller CNoutputs the WE signal having the active level to the NAND flash memoryN-k through the WE signal line B6-k.

[0244] Each of the NAND flash memories N-1 to N-n acquires the suppliedphysical address at the timing the level of the WE signal suppliedthereto changes to the active level, and stores the physical address inthe address register 25.

[0245] Although omitted in FIG. 13, the memory controller CN outputs onephysical address over four times, likewise the first embodiment.

[0246] Afterwards, the memory controller CN outputs data to be written,to the NAND flash memories N-1 to N-n through the data/address bus ofthe bus B7 one byte by one.

[0247] At this time, the memory controller CN outputs a WE signal havingan active level to the NAND flash memories N-1 to N-n through the WEsignal lines B6-1 to B6-n, each time it outputs data, as shown in FIG.13.

[0248] Thus, each of the NAND flash memories N-1 to N-n acquires thesupplied data at the timing the level of the WE signal changes to theactive level, and stores the acquired data in the data register 24.

[0249] After outputting the data to be written, the memory controller CNoutputs a write command (Com-W) to the NAND flash memories N-1 to N-nthrough the data/address bus of the bus B7, as shown in FIG. 13.

[0250] Also in this case, the memory controller CN outputs a CLE signalhaving an active level through the CLE signal line of the bus B7, and aWE signal having an active level through the WE signal lines B6-1 toB6-n to the NAND flash memories N-1 to N-n, likewise the above.

[0251] Each of the NAND flash memories N-1 to N-n responds to thesupplied write command at the timing the levels of the WE signal and CLEsignal change to the active level, and writes the data stored in thedata register 24 in the memory cell array 27.

[0252] Operations other than the above described are substantially thesame as those of the first embodiment.

[0253] Also in the way described above, same data can be writtenefficiently in the NAND flash memories N-1 to N-n.

[0254] According to the first and second embodiments, when outputting asame physical address to a plurality of NAND flash memories, the memorycontroller CN may control this physical address to be acquired in theplurality of NAND flash memories substantially at the same timing.

[0255] For example, when outputting a same physical address A1 to theNAND flash memories N-1 and N-n, the memory controller CN may controlthe physical address Al to be acquired in both of the NAND flashmemories N-1 and N-n at substantially the same timing.

[0256] Specifically, the memory controller CN according to the firstembodiment may output an ALE signal having an active level to both ofthe NAND flash memories N-1 and N-n through the ALE signal lines B2-1and B2-n at the timing of outputting the physical address A1, as shownin FIG. 14A.

[0257] Or, the memory controller CN according to the second embodimentmay output a WE signal having an active level to both of the NAND flashmemories N-1 and N-n through the WE signal lines B6-1 and B6-n at thetiming of outputting the physical address A1, as shown in FIG. 14B.

[0258] Due to this, the NAND flash memories N-1 and N-n acquire the samephysical address A1 at the same timing. As a result, the period of timefor supplying the physical address can be shortened, and thus writing ofdata can be more efficiently performed.

[0259] Further in a case where only a part of a physical address (forexample, the bottom 8 bits in the bit stream constituting a physicaladdress) is shared between a plurality of NAND flash memories, thememory controller CN may control the shared part of the physical addressto be acquired in the plurality of NAND flash memories substantially atthe same timing by performing the same operations as described above. Bythis control, the period of time for supplying the physical address canalso be shortened, and writing of data can be more efficientlyperformed.

[0260] Further, after step S414 of the data writing process shown inFIGS. 10A and 10B, the memory controller CN may again determine whetheror not writing of data is successful. Then, in a case where it isdetermined that writing of data is unsuccessful, the memory controllerCN may perform the processes of steps S411 to S414. Due to this, writingof data can be performed even in a case where postnatally defectiveblocks are consecutively discovered.

[0261] And in a case where it is determined in step S416 of the datawriting process shown in FIGS. 10A and 10B that not all the data hasbeen written, the memory controller CN may determine whether or not anyblock in which data can be stored remains in each of the NAND flashmemories N-1 to N-n. Specifically, the memory controller CN may refer tothe good block table, and determine whether or not there is any goodblock whose block address is the second smallest. Then, in a case wherethere is any NAND flash memory which has no block left in which data canbe written, the memory controller CN may suspend the data writingprocess. Or, the memory controller CN may suspend the data writingprocess for only the NAND flash memory which has no block left in whichdata can be written.

[0262] Further, in the data writing process shown in FIGS. 10A and 10B,the memory controller CN may perform the processes of steps s409 to S414separately for the data area constituting each page, and the redundantarea constituting each page. By doing so, after determining whether ornot writing of data in the data area is successful, the memorycontroller CN can write data in the redundant area regardless of thedetermination result. In other words, regardless of whether theobjective block is a postnatally defective block or not, data can bewritten in the redundant area of each page included in the objectiveblock. Therefore, a special flag, etc. can be written in the redundantarea.

[0263] Furthermore, the initial value of the variable DATA# to be set instep S402 of the data writing process shown in FIGS. 10A and 10B may notbe “0”.

[0264] And in steps S404 and 408 of the data writing process shown inFIGS. 10A and 10B, the values of the variable DATA# and variable PAGE#may be decremented, instead of being incremented.

[0265] Still further, the number of blocks included in the memory cellarray 27, the number of pages included in one block, and the number ofmemory cells constituting the memory cell arrays are not limited to thenumbers described in the above embodiments, but are arbitrary.

[0266] And when writing data, the memory controller CN divides onephysical address into four parts, and then outputs those partsseparately, as described above. However, the memory controller CN mayoutput one physical address without dividing it, or may output onephysical address after dividing it into two, three, or more than four.

[0267] And the 4096 blocks may be classified into a plurality of groups(zones). Zone addresses may be given to the plurality of zones seriallyfrom the top zone, and block addresses may be given to the plurality ofincluded blocks serially in each zone. In this case, the objective blockto be processed may be specified by a zone address and a block address.

[0268] Furthermore, according to the first and second embodiments, thedata to be written in the NAND flash memories N-1 to N-n is such data asbeing transmitted one byte by one, i.e., data having a so-called byteserial structure. However, data to be written in the NAND flash memoriesN-1 to N-n may be serial data to be transmitted one bit by one.

[0269] Yet further, the memory controller CN may obtain data to bewritten in the NAND flash memories N-1 to N-n by following an operationof an operator, by reading from a recording medium installed thereto, orby acquiring from foreign system through a communication line.

[0270] In this case, the memory controller CN comprises a keyboard, arecording medium driver for reading data from a recording medium, and aninput unit including a serial port, etc, for communicating with aforeign system. The recording medium driver may be a flexible disk drivedevice, or a MO (Magneto Optical disk) drive device, for example.

[0271] Further, each of the NAND flash memories N-1 to N-n may beconstituted by an AND flash memory (for example, “HN29W12811”(HITACHI)).

[0272] Further, each of the NAND flash memories N-1 to N-n may beconstituted by a flash memory which is switched between an enable stateand a disable state in accordance with a chip enable (CE) signal. Inthis case, the memory controller CN may control a physical address to beacquired in each of the NAND flash memories N-1 to N-n using a CE signalinstead of an ALE signal.

[0273] The NAND flash memories N-1 to N-n may be flash memories whichcan be controlled to acquire a physical address only by a WE signal. Inthis case, the memory controller CN may control a physical address to beacquired in each of the NAND flash memories N-1 to N-n without using anALE signal, but using a WE signal.

[0274] The structure of the flash memory writing apparatus according tothe embodiments of the present invention can be applied in various wayswithin the scope of the meaning of the present invention.

[0275] The embodiments of the present invention have been explained asabove. The data writing apparatus according to the present invention canbe realized by an ordinary computer system, not by a specially-madesystem. For example, the flash memory writing apparatus for performingthe above processes can be structured by installing a program forexecuting the above described operations of the memory controller CN ina computer to which NAND or AND flash memories are connected.

[0276] Such a program may be installed in a computer from a recordingmedium such as a flexible disk, a CD-ROM, etc.

[0277] Such a program may be posted on a bulletin board (BBS) on acommunication network, and may be distributed through a communicationline.

[0278] Or, such a program may be transmitted on a carrier wave(modulated wave) which is modulated by a signal representing thisprogram. An apparatus receiving this modulated wave may demodulate themodulated wave, and thus restore the program.

[0279] The program, which is installed in a computer, is executed underthe control of an OS (Operating System) likewise other applicationprograms. Due to this, the processes shown in the first and secondembodiments can be performed.

[0280] In a case where the OS shares some parts of the processes, or theOS constitutes a part of a component included in the present invention,a program from which those parts are excluded may be stored in arecording medium. Also in this case, according to the present invention,a program for realizing each function and step performed by a computeris stored in the recording medium.

[0281] This application is based on Japanese Patent Application No.2001-301789 filed on Sep. 28, 2001 and including specification, claims,drawings and summary. The disclosure of the above Japanese PatentApplication is incorporated herein by reference in its entirety.

1. A data writing apparatus for writing same data in a plurality ofstorage devices, wherein each of said plurality of storage devices (N-1to N-n) comprises: a plurality of memory blocks which store data anderror information representing whether or not each of said plurality ofmemory blocks is a good block which can store data correctly; an errorinformation supplier (22, 34, 35) which supplies said data writingapparatus with the error information stored in said plurality of memoryblocks; and a data writer (22, 34, 35) which, in response to aninstruction of said data writing apparatus, writes data in a memoryblock designated by said data writing apparatus, and said data writingapparatus comprises: a block designator (12) which designates a memoryblock to which data is to be written for each of said plurality ofstorage devices (N-1 to N-n), based on the error information suppliedfrom said error information supplier (22, 34, 35); a data supplier (12)which supplies said plurality of storage devices (N-1 to N-n) with datato be written; and a writing instructor (12) which instructs saidplurality of storage devices (N-1 to N-n) to write the data supplied bysaid data supplier (12) in the memory blocks designated by said blockdesignator (12).
 2. The data writing apparatus according to claim 1,wherein each of said plurality of storage devices (N-1 to N-n) furthercomprises: a first determiner (22, 34, 35) which determines whether ornot the data has been written correctly; and a result supplier (22, 34,35) which supplies said data writing apparatus with a determinationresult of said first determiner (22, 34, 35), said data writingapparatus further comprises: a second determiner (12) which determineswhether or not there is any defective device among said plurality ofstorage devices (N-1 to N-n) to which the data has not been writtencorrectly, based on the determination result supplied form said resultsupplier (22, 34, 35); and a defective device identifier (12) which in acase where said second determiner (12) determines that there is anydefective device, identifies the defective device, said block designator(12) designates another memory block to which the data is to be written,in the defective device identified by said defective device identifier(12) based on the error information, and said writing instructor (12)instructs the defective device to write the data supplied by said datasupplier (12) in the another memory block designated by said blockdesignator (12).
 3. The data writing apparatus according to claim 2,wherein said block designator (12) comprises: a table generator (12)which generates a good block table listing good blocks included in eachof said plurality of storage devices (N-1 to N-n), based on the errorinformation supplied from said error information supplier (22, 34, 35);and a block determiner (12) which determines a memory block to which thedata is to be written, based on the good block table.
 4. The datawriting apparatus according to claim 2, wherein said data writingapparatus further comprises an information updating unit (12) which, ina case where said second determiner (12) determines that there is anydefective device, updates the error information stored in said pluralityof memory blocks included in the defective device.
 5. The data writingapparatus according to claim 2, further comprising: a third determiner(12) which determines whether or not there is any storage device whichhas no memory block left in which data can be written; and a suspensionunit (12) which suspends data writing, in a case where said thirddeterminer (12) determines that there is any storage device which has nomemory block left in which data can be written.
 6. The data writingapparatus according to claim 2, wherein: each of said plurality ofmemory blocks is allotted an address; and said block designator (12)designates a memory block to which data is to be written, by outputtingan address allotted to the memory block to which data is to be written.7. The data writing apparatus according to claim 6, wherein said blockdesignator (12) divides the address into a plurality of parts, andoutputs the plurality of parts one by one.
 8. The data writing apparatusaccording to claim 6, wherein in a case where at least a part of theaddress to be output is common to at least two of said plurality ofstorage devices (N-1 to N-n), said block designator (12) outputs thecommon part of the address to said at least two storage devicessimultaneously.
 9. The data writing apparatus according to claim 2,wherein each of said plurality of storage devices (N-1 to N-n) isconstituted by a NAND type flash memory.
 10. The data writing apparatusaccording to claim 2, wherein each of said plurality of storage devices(N-1 to N-n) is constituted by an AND type flash memory.
 11. A datawriting method of writing same data in a plurality of storage devices,wherein each of said plurality of storage devices (N-1 to N-n)comprises: a plurality of memory blocks which store data and errorinformation representing whether or not each of said plurality of memoryblocks is a good block which can store data correctly; and a data writer(22, 34, 35) which writes data in said plurality of memory blocks, andsaid data writing method comprises: a block designating step ofdesignating a memory block in which data is to be written for each ofsaid plurality of storage devices (N-1 to N-n), based on the errorinformation stored in said plurality of memory blocks; a data supplyingstep of supplying said plurality of storage devices (N-1 to N-n) withdata to be written; and a writing step of instructing said plurality ofstorage devices (N-1 to N-n) to write the data supplied in said datasupplying step in the memory block designated in said block designatingstep.
 12. A program for controlling a computer to function as a datawriting apparatus which writes same data in a plurality of storagedevices (N-1 to N-n) each comprising: a plurality of memory blocks whichstore data and error information representing whether or not each ofsaid plurality of memory blocks is a good block which can store datacorrectly; an error information supplier (22, 34, 35) which supplies theerror information stored in said plurality of memory blocks; and a datawriter (22, 34, 35) which writes data in said plurality of memoryblocks, said data writing apparatus comprising: a block determiner (12)which determines a memory block to which data is to be written for eachof said plurality of storage devices (N-1 to N-n), based on the errorinformation supplied from said error information supplier (22, 34, 35);a data supplier (12) which supplies said plurality of storage devices(N-1 to N-n) with data to be written; and a writer (12) which, bycontrolling each of said plurality of storage devices (N-1 to N-n),writes the data supplied by said data supplier (12) in the memory blockdetermined by said block determiner (12).